Prof.(Dr.) Jaydeb Bhaumik

Designation : Professor

Phone No. : 03224-250900 Extn:229
Email : bhaumik.jaydeb@gmail.com

 

Contact Details : 

Head, Department of Electronics & Communication Engineering, Haldia Institute of Technology, ICARE Complex, Hatiberia, Haldia, West Bengal, 721657

https://scholar.google.co.in/citations?user=VKOBoQYAAAAJ&hl=en

http://dblp.uni-trier.de/pers/hd/b/Bhaumik:Jaydeb

https://www.researchgate.net/profile/Jaydeb_Bhaumik/citations

http://www.dak.iitkgp.ernet.in/phd/profile.php?roll=06GS9404

 

Education

Ph.D. (Engg.), IIT Kharagpur

M.Tech, University of Calcutta

B.Tech, University of Calcutta

 

 

Skills

Technical:

Xilinx tools, MATLAB, LATEX

Other Skills:

Experience
  • Teaching:  11.25 years
  • Research:  4.5 years
  • Industry:  NA

 

Course Taught

Odd Semester 2015-16

Analog Communication Lab (EC-591)

Course Home

Elective Theory (MVLSI-302)

Course Home

Even Semester 2015-16

Digital Communications (EC-601)

Course Home

Digital Communications Lab (EC-691)

Course Home

Low Power VLSI Design (MVLSI-205B)

Course Home

 
Areas of Research

VLSI architecture for cryptographic algorithms & error correcting codes, Security issues in image processing, Light weight block cipher, Cellular Automata

Membership of Professional Bodies
  • IEEE Member (No. 90443601) since 2007
  • Cryptology Research Society of India (CRSI) Life Member (No. L/0528) since 2008
  • International Association for Engineers (No. 158556) since 2015
  • The Society of Digital Information and Wireless Communications (ID: 11742)
Publications

Journals:

[1]

J. Samanta, J. Bhaumik and S. Barman, “Compact CA-based Single Byte Error Correcting Codec,” IEEE Transactions on Computers, Aug. 2017 (SCI, Accepted).

[2] G. Maity, J. Bhaumik, and A. Kundu, “A New SPN Type Architecture to Strengthen Block Cipher against Fault Attack,” International Journal of Network Security (Accepted) (Scopus)
[3] T. Hassan, J. Samanta and J. Bhaumik, “FPGA and ASIC Implementation of Different Finite Field Multipliers for Forney Block,” Journal of Active and Passive Electronic Devices, Old City Publishing (Accepted). (ESCI)
[4] J. Samanta, J. Bhaumik and S. Barman, “FPGA and ASIC Implementation of RS (47, 41) Codec for Intelligent Home Networking System,” Journal of Active and Passive Electronic Devices, Old City Publishing (in press). (ESCI)
[5] J. Samanta, J. Bhaumik and S. Barman, “FPGA based Area Efficient RS (23, 17) Codec,” Journal of Microsystem Technologies, Springer, vol. 23, no. 3, pp.639-650, Mar. 2017 (SCI).
[6]

J. Samanta, M. Suman, J. Bhaumik and S. Barman, “A Transistor Level Implementation of Reed Solomon Encoder in GF(28) ,” Journal of Active and Passive Electronic Devices, Old City Publishing, vol. 11, no. 2-3, pp. 243-261, Apr. 2016 

[7]

J. Samanta, J. Bhaumik and S. Barman, “CA-based Area Optimized Three Bytes Error Detecting  Codes ,” Journal of Cellular Automata, vol. 10, no. 5-6, pp. 409-423, Oct. 2015  (SCI)

[8]

J. Samanta, J. Bhaumik and S. Barman, “A modified Karatsuba multiplier for ‘key equation solver’ in RS code,” Journal of Radioelectronics and Communications Systems, Springer, vol. 58, no. 10, pp. 452-461, Oct. 2015 (SCImago)

[9]

M. Suman, J. Samanta, D. Chowdhury and J. Bhaumik, "Relative Performance Analysis of Different CMOS Full Adder Circuits," Int. Journal of Computer Applications, vol. 114, no. 6,  pp. 8-14, March 2015.

[10]

S. De  and J. Bhaumik, "An AES-based Robust Image Encryption Scheme," Int. Journal of Computer Applications, vol. 109,  no. 12,  pp. 29-34, Jan. 2015.

[11]

S. De and J. Bhaumik, “TBLT-AES: A Robust Image Encryption Scheme,” Journal of Discrete Mathematical Sciences & Cryptography, (Taylor & Francis, Co-published with TARU Publications) vol. 17, no. 3, pp. 273-288, Sept. 2014. (SCImago)

[12]

J. Samanta and J. Bhaumik, “Comments On VLSI Implementation of Reed Solomon Encoder Algorithm For Communication Systems” Journal of Radioelectronics and Communications Systems, Springer, vol. 57, no. 7, pp. 331-332, July 2014. (SCImago)

[13]

S. Das and J. Bhaumik, “A Fault Based Attack on MDS-AES”  International Journal of  Network Security, vol.16, no.3, pp.193-198, May 2014. (SCImago)

[14]

S. Jana, J. Bhaumik and M. K. Maiti, “Survey on Lightweight Block Cipher,” International Journal of Soft Computing and Engineering, vol. 3, no. 5, pp. 183-187, Nov. 2013.

[15]

J. Bhaumik, D. Mukhopadhyay and D. Roy Chowdhury, “Rain: Reversible Addition with Increased Nonlinearity,” International Journal of Network Security, vol. 15, no. 4, pp. 298-306, July 2013. (SCImago)

[16]

A. S. Das , S. Das and J. Bhaumik, “Design of RS (255, 251) Encoder and Decoder in FPGA,” International Journal of Soft Computing and Engineering, vol. 2, no. 6, pp. 391-394, Jan. 2013.

[17]

J. Bhaumik, A. S. Das and J. Samanta, “Architecture for Programmable Generator Polynomial Based Reed-Solomon Encoder and Decoder,” International Journal of Soft Computing and Engineering, vol. 2, no. 6, pp. 395-399, Jan. 2013.

[18]

B. Jana, P. Pal and J. Bhaumik, “New Image Noise Reduction Schemes Based on Cellular Automata,” International Journal of Soft Computing and Engineering, vol. 2,      no. 2, pp. 98-103, May 2012.

[19]

J. Bhaumik and D. Roy Chowdhury, “Nimix: An Involutary Nonlinear Vectorial  Boolean Function,” Journal of Discrete Mathematical Sciences & Cryptography, (Taylor & Francis,Co-published with TARU Publications), vol. 14, no. 3, pp. 261-277, June 2011. (SCImago)

[20]

J. Bhaumik and D. Roy Chowdhury, “New Architectural Design of CA-Based Codec,” IEEE Transactions on Very Large Scale Integration Systems, vol. 18, no. 7, pp. 1139-1144, July 2010. (SCI)

[21]

J. Bhaumik and D. Roy Chowdhury, “An Integrated ECC-MAC Based on RS Code,” Transactions on Computational Science, Springer, vol. 4, LNCS 5430, pp. 117-135, Apr.  2009.

Conferences:

[1] T. Sinha and J. Bhaumik, “Designing of Sharp Transition Low Pass FIR Filter using Multistage FRM Approach,” 2nd Int. conf. on “Devices for Integrated Circuit (DevIC 2017), Kalyani Govt. Engg. College, March 2017, pp. 1-4.
[2] P. Mitra and J. Bhaumik, “Pre-Layout Decap Allocation for Power Supply Noise Suppression and Performance Analysis of 512-point FFT core,” 2nd Int. conf. on “Devices for Integrated Circuit (DevIC 2017), Kalyani Govt. Engg. College, March 2017, pp. 1-5.
[3] J. Samanta, J. Bhaumik and S. Barman, “Area Optimized SEC-DED Codec for Computer Memory,” 5th Int. Conf. on Computing, Communication and Sensor Network, (CCSN2016), Kolkata, ISBN No.:81-85824-46-0, Dec. 2016, pp.159-163.
[4] J. Bhaumik and S. De,“A Symmetric Key Based Image Encryption Scheme,” Int. Conference on Computing and Communication Systems(I3CS 2016), North Eastern Hill University, Shillong, Nov. 2016, pp. 1-8
[5]

P. Mitra, J. Bhaumik and C. Roy Chowdhury, “Pre-Layout  Noise suppression and Delay estimation with decap allocation for FFTcore,” 3rd International Conference on Microelectronics, Circuits and Systems, MAKAUT, Kolkata, July 2016, pp. 128-132.

[6]

S. De and J. Bhaumik, “An Advanced Encryption Standard Based Algorithm for Image Encryption,” Int.  Conference of Computing and Communication Systems, North Eastern Hill University, Shillong, April 2015, pp. 97-102. 

[7]

J. Bhaumik, "Technical Report:Synthesis of all Maximum Length Cellular Automata of Cell Size up to 12," March 2015,  available in arxiv-web3.library.cornell.edu/pdf/1503.04006

[8]

J. Samanta, J. Bhaumik and S. Barman, “Compact RS(32, 28) Encoder,” 1st Int. Conf. on Intelligent Computing & Applications(ICICA), NIT Durgapur, Advances in Intelligent Systems and Computing, Springer, vol. 343, Feb. 2015, pp. 89-95. 

[9]

G. Maity and J. Bhaumik, “New Hybrid CA Rule Sets for Cryptographic Design,” Int. conf. on Computer, Communication, Control and Information Technology, AOT Hoogly, IEEE Xplore, Feb. 2015, pp. 1-5. 

[10]

J. Samanta, J. Bhaumik and S. Barman, “Low Complexity 3-Symbol Error Detecting RS(23, 17) Code,” 3rd Int. Conf. on Computing, Communication and Sensor Network, Puri, India, Dec. 2014, pp. 30-36. 

[11]

J. Bhaumik and D. Roy Chowdhury “HDNM8: A Round-8 High Diffusion Block Cipher With Nonlinear Mixing Function,”  Int. Conf. on Mathematics and Computing (ICMC), Haldia, India, Chapter 4, Proceedings in Mathematics and Statistics 91, Springer, Aug. 2014, pp. 41-55.

[12]

J. Samanta, R. Sultana and J. Bhaumik “FPGA based Modified Karatsuba Multiplier,” Int. Conf. on VLSI and Signal Processing (ICVSP), IIT Kharagpur, Jan. 2014, pp. 1-6. 

[13]

A.  K.  Singh, J. Samanta and J. Bhaumik, “Modified I-V Model for Delay Analysis of UDSM  CMOS Circuits,”  Int. Conf. on Communications, Devices and Intelligent Systems (CODIS), Jadavpur University, Kolkata, Dec. 2012, IEEE Xplore, pp. 357-360.

[14]

S. Das and J. Bhaumik, “Strengthening SPN-type Block Cipher Architecture Against Fault Attack,” Int. Conf. on Communications, Devices and Intelligent Systems (CODIS), Jadavpur University, Kolkata, Dec. 2012, IEEE Xplore, pp. 560-563.

[15]

J. Bhaumik and D. Roy Chowdhury “Design and Implementation of Cellular Automata Based Diffusion Layer for SPN-type Block Cipher,” Int. Conf. on Informatics, Electronics & Vision 2012 (ICIEV12), Bangladesh, May 2012, pp. 828-831. 

[16]

S. Das and J. Bhaumik, “Compact Implementation of AES on FPGA,” 1st National Conf.     on Advanced Communication Systems and Design Techniques, Haldia, West Bengal, Nov. 2011, pp. 62-65

[17]

J. Bhaumik and D. Roy Chowdhury, “CA-based Diffusion Layer for an SPN-type Block Cipher” 17th Int. Workshop on Cellular Automata and. Discrete Complex Systems (AUTOMATA 2011), Chile, Nov. 2011, pp. 243-251, ISBN  978-2-905267-79-5.

[18]

J. Bhaumik and D. Roy Chowdhury, “Key Mixing in AES through Nimix,” 10th National Workshop on Cryptology, PSG College of Technology, Coimbatore, India,    Sep. 2010, pp. 118-124.      

[19]

J. Bhaumik, D. Roy Chowdhury and I. Chakrabarti, “Null Boundary 90/150 Cellular Automata for Multi-byte Error Correcting Code,” Int. Conf. on Cellular Automata for Research and Industry (ACRI), Italy, Sep. 2010, LNCS 6350, pp. 231-240.

[20]

J. Bhaumik, D. Mukhopadhyay and D.  Roy Chowdhury, “Smix: A New Highly Non-linear Reversible Boolean Function,” 9th National Workshop on Cryptology, NIT Surat, India, Aug. 2009, pp. 47-52.

[21]

J. Bhaumik, and D. Roy Chowdhury, “Nmix: An Ideal Candidate For Key Mixing,”  Int. Conf. on Security and Cryptography (Secrypt), Milan, Italy, July 2009, pp. 285-288.

[22]

J. Bhaumik, B. Janakiram and D. Roy Chowdhury, “Architectural Design of CA-Based Double Byte Error Correcting Codec,” 3rd Int. Conf. on Industrial and Information Systems (ICIIS), IIT Kharagpur, India, Dec. 2008, IEEE Xplore, pp. 1-6.

[23]

J. Bhaumik, D. Roy Chowdhury and I. Chakrabarti, “An Improved Double Byte Error Correcting Code using Cellular Automata,” 8th Int. Conf. on Cellular Automata for  Research and Industry (ACRI 2008), Japan, Sep. 2008, LNCS 5191,  pp. 463-470.

[24]

J. Bhaumik “Nimix: Nonlinear Involutary Key Mixing Function,” 8th National Workshop on Cryptology, University of Hyderabad, India, Aug.  2008, pp. 87-94.

[25]

J. Bhaumik, D. Roy Chowdhury and I. Chakrabarti, “Design and Implementation of RS (32, 28) Encoder and Decoder using Cellular Automata,” 15th Int. Conf. on Advanced Computing and Communications, IIT Guwahati, India, Dec. 2007, IEEE Computer Society, pp. 491-496.   

[26]

J. Bhaumik and D. Roy Chowdhury, “An Integrated Approach for Message Authenticated Error Correcting Code,” 7th National Workshop on Cryptology, Amrita Vishwa Vidyapeetham, Coimbatore, India, Aug. 2007, pp. 76-84.

[27]

J. Bhaumik, A. K. Mandal and A. K. Nath. “Use of Vector Sensor in the Smart Antenna for the Mobile and Handheld Devices in 4G,” Proc. of National Conference on Recent Trends in Information Systems(ReTIS-06), Jadavpur University, Kolkata, India, July 2006, pp. 144-147.

[28]

J.  Bhaumik and A. K. Nath, “Cell Telephony with Smart Antenna – The Most Viable Communication Technology for Rural Development Initiatives,” Proc. of 37th MID TERM SYMPOSIUM-06 on Information Communication Technology Initiative for Rural Developments, Kolkata, India, April 2006, pp. 1-7.

Books:

[1]

J. Bhaumik  and  S. Das, “Substitution and Permutation Network Type Block Cipher: Design and Implementation,” LAP LAMBERT Academic Publishing, Germany, ISBN 978-3-659-49238-9, Nov. 2013

[2]

J. Bhaumik and A.  S. Das, “Programmable Reed-Solomon Codec: Design and Implementation,” LAP LAMBERT Academic Publishing, Germany, ISBN 978-3-659-45726-5, Sept.2013

Guided Projects B.Tech/ M.Tech/ Ph.D

B.Tech

 

M.Tech

List of Graduated M. Tech. Students

1. Tarique Hassan (2014-2016)
2. Mandira Sahu (2014-2016)
3. Pallavi Panda (2013-2015)
4. Rita Dutta (2012-2014)
5. Nikhil Nag-banshi (2011-2013)
6. Anindya Sundar Das (2010-2012)
7. Niladree De (2010-2012)
8. Satyajit Das (2010-2012)

 

Ph.D

List of Current Ph.D Students

1. Jagannath Samanta
2. Supriyo De
3. Partha Mitra
4. Pabitra Paul

 

 

Sponsored Projects/Grants

Analysis and Design of SPN-type Block Cipher, Fast Track Young Scientist Scheme of SERB, DST, Govt. of India