Mr. Jagannath Samanta
(Ph.D thesis submitted)

Designation : Assistant Professor (PB-II)

Phone No. : 03224-250900 Extn:361
Email : jagannath19060@gmail.com

 

Contact Details : 

Faculty Room-4, Department of Electronics & Communication Engineering, Haldia Institute of Technology, ICARE Complex, Hatiberia, Haldia, Phone no. 9733630232, West Bengal, 721657

Google Schoolar: https://scholar.google.co.in/citations?user=Tr8HUPUAAAAJ&hl=en

Research Gate: https://www.researchgate.net/profile/Jagannath_Samanta/publications

DBLP: http://dblp.uni-trier.de/pers/hd/s/Samanta:Jagannath

 

Education

Ph.D. (Thesis Submitted), University of Calcutta

M.Tech, West Bengal University of Technology

B.Tech, West Bengal University of Technology

 

 

Skills

Technical:

Xilinx, Mentor Graphics, Cadence, Tanner Spice, MATLAB

Other Skills:

Verilog, VHDL, MS office

Experience
  • Teaching:  12.5 years Teaching experience
  • Research:  1 year Research experience
  • Industry:  six month

 

Course Taught

Odd Semester 2015-16

Digital IC Design (MVLSI-103)

Course Home

CAD Tools for VLSI Design (MVLSI-191)

Course Home

Basic Electrical and Electronics engg.-I (ES-101)

Course Home

Basic Electronics engg. -I Lab (ES-191)

Course Home

Even Semester 2015-16

Information Theory & Coding (EC-604B)

Course Home

Physical Design & Testing (MVLSI-204D)

Course Home

Design Lab (EC-881)

Course Home

 
Areas of Research

Digital VLSI Design, VLSI architecture for Error Correcting Codes, Storage or Memory Systems, Cellular Automata, Cryptography

Membership of Professional Bodies

1. Member of ''The Institution of Engineers (India)' (Membership No: M-1591066), August, 2017.

2.Associate member of Universal Association of Computer and Electronics Engineers (UACEE) (Membership ID: AM10100052323).

3.The Society of Digital Information and Wireless Communications (SWIC) (Membership ID: 11741)

4.International Association of Engineers (IAENG)- (Membership ID: 158527)

5. Editorial Board Member of ACE Journal of Electronics and Communications

 

Publications

Journals:

[1]

J. Samanta, J. Bhaumik, S. Barman, Compact CA-based Single Byte Error Correcting Codec, IEEE Transctions on Computers, vol.67, no.2, pp.291-299, Aug- 2017 (SCI, Impact Factor: 2.916),  DOI 10.1109/TC.2017.2739726.

[2]

J. Samanta, J. Bhaumik and S. Barman, “FPGA and ASIC Implementation of RS (47, 41) Codec for Intelligent Home Networking System,” Journal of Active and Passive Electronic Devices, Old City Publishing (in press). (ESCI)

[3]

T. Hassan, J. Samanta and J. Bhaumik, “FPGA and ASIC Implementation of Different Finite Field Multipliers for Forney Block,” Journal of Active and Passive Electronic Devices, Old City Publishing (Accepted). (ESCI)

[4]

J. Samanta, J. Bhaumik and S. Barman, “FPGA based Area Efficient RS(23, 17) Codec”, Microsystems Technologies (Springer, SCIE, IF-0.974), vol.22, no.7, pp.1-12, 2016.

[5]

J. Samanta, J. Bhaumik and Soma Barman, A transistor level implementation of Reed Solomon encoder in GF(28), in Journal of active and passive electronics devices (Old City Publishing), vol:11, no.2-3, pp:243-261, 2016.

[6]

J. Samanta, J. Bhaumik and S. Barman, CA-based Area Optimized Three Bytes Error Detecting Codes, in Journal of Cellular Automata (Old City Publishing), (SCI Expanded, IF-0.698) vol.10, no.5-6, pp:409-423, Oct.-2015. ISSN: 1557-5969.

[7]

J. Samanta, J. Bhaumik and S. Barman, MODIFIED KARATSUBA MULTIPLIER FOR ‘KEY EQUATION SOLVER’ IN RS CODE, in Radioelectronics and Communications Systems Journal (Springer), vol.58, no.10, pp:452-461, 2015. (SCImago, IF-0.19).

[8]

M. Suman, J. Samanta, D. Chowdhury and J. Bhaumik., “Relative Performance Analysis of Different CMOS Full Adder Circuits”, International Journal of Computer Applications, vol.114, no. 6, pp:8-14, March 2015., 973-93-80885-73-1.

[9]

J. Samanta and J. Bhaumik, “Comments On VLSI Implementation Of Reed-Solomon Encoder Algorithm For Communication Systems” in Radioelectronics and Communications Systems Journal (Springer), vol. 57, no. 7, pp:331-332,July,2014. (SCImago, IF-0.19).

[10]

R. Sultana and J. Samanta,Comparison of different design techniques of XOR & AND gate using EDA simulation tool”, International Journal of VLSI and Embedded Systems (IJVES), ISSN: 2249–6556, Vol-04, Issue-03, pp:343-349, May - June 2013

[11]

M. Basak, M. Sutradhar, B. Santra, M. Saha, D. Chowdhury and J. Samanta, “Study the performance analysis of low power –high speed carry select adder using EDA simulation tool”, International Journal of VLSI and Embedded Systems (IJVES), ISSN: 2249–6556, Vol-04, Article-06102, pp:444-448, June 2013.

[12]

J. Samanta, M. Halder, B. P. De, Performance Analysis of High Speed Low Power Carry Look-Ahead Adder Using Different Logic Styles” International Journal of Soft Computing and Engineering (IJSCE) ISSN: 2231-2307, Volume-2, Issue-6, pp:330-336, Jan- 2013.

[13]

Bhaumik, A. S. Das and J. Samanta, Architecture for Programmable Generator Polynomial Based Reed-Solomon Encoder and Decoder” International Journal of Soft Computing and Engineering (IJSCE) ISSN: 2231-2307, Volume-2, Issue-6, pp:395-399, Jan- 2013.

[14]

J. Samanta, A Patra, D Mishra, R Rashmi, I Kundu & R Koley, Performance Analysis of Different Topologies of 1-Bit Full Adder in UDSM Technology”, International Journal of Innovative Technology and Exploring Engineering (IJITEE) ISSN: 2278-3075, Volume-1, Issue-2, pp:35-42, July-2012.

[15]

J. Samanta, B. P. De, B. Bag & R. K. Maity, “Comparative study for delay & power dissipation of CMOS Inverter in UDSM range”, International Journal of Soft Computing and Engineering (IJSCE), ISSN: 2231-2307,Volume-1, Issue-6, pp:162-167,January2012.

[16]

R. K. Maity, J. Samanta, “Construction and performance studies of a pseudo-orthogonal code for fiber optic CDMA LAN”, International Journal of Soft Computing and Engineering (IJSCE), ISSN: 2231-2307, Volume-1, Issue-6, pp: 196-201, January 2012.

[17]

B P De and J. Samanta, “Thermal bound placement with wire length consideration for standard cells in VLSI”, IJCSI International Journal of Computer Science Issues, Special Issue, ICVCI-2011, Vol. 1, Issue 1, pp:19-22, ISSN (Online): 1694-0814, November 2011.

Conferences:

[1]

Jagannath Samanta, Jaydeb Bhaumik, Soma Barman and Raj Kumar Maity, “Binary error correcting codes for DNA databank,” Proc. in Int. Conf. on Communication, Devices and Computing (ICCDC2017), (accepted), (Lecture Notes in Electrical Engineering (LNEE),Springer Book Series). (Paper Presented).

[2]

Jagannath Samanta, Jaydeb Bhaumik, Soma Barman, Sk. Golam S. Hossain, Mandira Sahoo and Subrata Dutta, “RS(255, 249) codec based on all primitive polynomials over GF(28),” Proc. in Int. Conf. on Communication, Devices and Computing (ICCDC2017), (accepted), (Lecture Notes in Electrical Engineering (LNEE), Springer Book Series). (Paper Presented).

[3]

Arghyadeep Sarkar, Jagannath Samanta, Amartya Barman and Jaydeb Bhaumik, “FPGA Implementation of OLS (32, 16) Code and OLS (36, 20) Code”, Proc. in Int. Conf. on Communication, Devices and Computing (ICCDC2017), (accepted), (Lecture Notes in Electrical Engineering (LNEE), Springer Book Series).

[4]

Jagannath Samanta, Jaydeb Bhaumik, Soma Barman and Raj Kumar Maity, “Binary error correcting codes for DNA databank,” Proc. in Int. Conf. on Communication, Devices and Computing (ICCDC2017), (accepted), (Lecture Notes in Electrical Engineering (LNEE),Springer Book Series).

[5]

Jagannath Samanta, Jaydeb Bhaumik, Soma Barman, Sk. Golam S. Hossain,  Mandira Sahoo and Subrata Dutta, “RS(255, 249) codec based on all primitive polynomials over GF(28),” Proc. in Int. Conf. on Communication, Devices and Computing (ICCDC2017), (accepted), (Lecture Notes in Electrical Engineering (LNEE), Springer Book Series).

[6]

Arghyadeep Sarkar, Jagannath Samanta, Amartya Barman and Jaydeb Bhaumik, “FPGA Implementation of OLS (32, 16) Code and OLS (36, 20) Code”, Proc. in Int. Conf. on Communication, Devices and Computing (ICCDC2017), (accepted), (Lecture Notes in Electrical Engineering (LNEE), Springer Book Series).

[7]

J. Samanta, J. Bhaumik and S. Barman, “Area Optimized SEC-DED Codec for Computer Memory,” 5th Int. Conf. on Computing, Communication and Sensor Network, (CCSN2016), Kolkata, ISBN No.:81-85824-46-0, Dec. 2016, pp.159-163.

[8]

J. Samanta, J. Bhaumik & S. Barman, “COMPACT RS(32, 28) ENCODER” Proc. of 1st Int. Conf. Intelligent Computing & Applications (ICICA 2014), NIT DGP,  (Published by SpingerLink, Advances in Intelligent Systems and Computing Vol.-343, Feb 2015, pp. 89-95.)

[9]

J. Samanta, J. Bhaumik & S. Barman, “Low Complexity 3-Symbol Error Detecting RS(23, 17) Code”. 3rd Int. Conf. on Computing, Communication and Sensor Network, (CCSN2014), PIET, Odshia, ISBN No.:81-85824-46-0, pp:30-37.(Paper Presented).

[10]

J. Samanta, R. Sultana & J. Bhaumik, “FPGA Based Modified Karatsuba Multiplier” International Conf. on VLSI and Signal Processing (ICVSP14-IEEE Sponsored) at IIT KGP, Jan. 2014, pp:1-6.(Paper Presented).

[11]

J Samanta and B P De, “Delay analysis of UDSM CMOS VLSI circuits”, International Conference ICCSTD-2011, Kerala, Procedia Engineering, Volume 30, 2012, (Science Direct) March-2012, pp:135-142. (Paper Presented)

[12]

A. K. Singh & J. Samanta, “Different Physical Effects in UDSM MOSFET for Delay & Power Estimation: A Review”, International Conference on Electrical, Electronics and Computer Science (SCEECS-2012), NIT Bhopal, ISBN-978-1-4673-1515-9/IEEE Explore, March-2012, pp:1-5.

[13]

J Samanta and B P De,“Comprehensive analysis of delay in UDSM CMOS circuits”, Proceeding of, ICECCT’11, Villupuram, Tamil Nadu, India, IEEE explore, 978-1-4577-1894-6/11, Nov-2011, pp:29-32. (Paper Presented)

[14]

R. Dasgupta, D. Saha, J. Samanta, S. Chatterjee, C. K. Sarkar, “Implementation of a New Offset Generator Block for the Low-Voltage, Low-Power Self Biased Threshold Voltage Extractor Circuit”, VDAT 2012: pp:156-165 (Published by SpingerLink, Lecture Notes in Computer Science, July-2012, Volume 7373/2012, 156-165

[15]

A.K. Singh, J. Samanta & J. Bhaumik, “Modified I-V Model for Delay Analysis of UDSM CMOS Circuits”, International Conference on Communications, Devices and Intelligent Systems (CODIS), Jadavpur University, 978-1-4673-4700-6/12, IEEE Explore, Dec-2012, pp:369-372. (Paper Presented)

Books:

[1]

J. Samanta, “UDSM CMOS Circuits: Delay and Power Models” Lap Lambert Academic Publishing, Germany, ISBN-978-3-659-52303-8, February-2014. Pages:97.

[2]

J. Samanta, A. K. Singh, “An improved MOSFET I-V model and its application in nano-CMOS circuits” Lap Lambert Academic Publishing, Germany, ISBN-978-3-659-44752-5, August-2013. Pages:72.

Guided Projects B.Tech/ M.Tech/ Ph.D

B.Tech

Sl No.

Name of the project

Name of students

Year

Remarks

1.

Design and power performance optimization of Memory using dual bit CAM cells

Abhishek Gupta, Rahin Biswas

2009

Internal guide (JU)

2.

An improved design of synchronous up/down counters with VLSI Technologies

Arnab Roy, Dipanjan Pradhan

2009

Internal guide (JU)

3.

Temperature Sensor

Rakesh Ranjan, Kumar Sundaram, Pankaj Kumar Prasad, Nishant Kumar

2010

 

4.

Mobile cell phone charger

Manish Kumar, Rahul Kumar, Uttam Kumar, Pradeep Kumar

2010

 

5.

Design & Construction of remote control fan regulator

Chayan kr. Dutta, Arpan Jana, Amit Dasgupta, Argha Das

2010

 

6.

Design and implementation of high speed Carry look ahead adder

Rachaita Chaklader, Lipika Barai, Bhaswati Sarkar

2011

 

7.

Design and implementation of 4 bit ALU

Souvik Bera, Sovona Jana, Subrajit Majumder, Supriyo Mondal

2011

 

8.

Analysis and Comparison of different topologies of Full Adder circuits in Submicron Technology

Anurag Mondal, Richa Rashmi,                        Ishika Kundu, Ritubritta Koley,                                                                      Diwakar Mishra, Swesh Kumar                                                                                                             

 

2012

 

9

 Performance Analysis Of

Carry Select Adder Using EDA

Simulation Tool

 Brijita Santra, Madhurima Saha,Moitri Sutradhar, Moumita Basak

2013

 

10

 Performance Comparison Of Combinational Circuits Using Static And Dynamic Logic

 Tanushri Banerjee, Mampi Bera

Sejuti Gupta, Rituparna Mandal

2014

 

11

Design Of Reed Solomon (255, 243) Encoder And Decoder Using Verilog

 

Ritesh Kumar, Rajni Kant Pandey,

Sucheta Biswas , Somnath Das

2015

 

12

FPGA and ASIC based implementation of single error correcting codec for DNA bases

Anunay Kumar, Raja Babu, Piyali Chakraborty, Vikash Kumar, Saptarshi Baisya

2016

 

13

Design and Implementation of SEC-DED Codec for Memory Applications

Akash Kewat, Megha Bhardwaj, Pawan Kumar, Pallavi Kumari

2017

 

14

Design and Implementation of triple error correcting (15, 5) BCH code

Sumit Agarwal, Sruti Priya, Sarabjit Singh

2017

 

15

Design and Implementation of OLS code

Arghayadeep Sarkar (Jalpaiguri Govt. College)

2017

 

16

Design and Implementation of Dutta Codes

Chandra Bhan

2018

 

17

Design of Neale DAEC Codec

Aman Raj

2018

 

 

M.Tech

Sl No.

Name of the project

Name of students

Year

Remarks

1.

Comparison of CNT & Copper interconnects and its applicability of CNT as future interconnects

Sandip Bhattacharya

2011

Internal guide (MSIT)

2.

Modeling of CNT FET in Verilog – AMS & applicability in future microelectronics circuits.

Subhajit Das

2011

Internal guide (MSIT)

3.

Comparative Study Of High Speed Carry Look Ahead Adder Using Different Logic Styles

Mousam Halder

2012

 

4.

a simple & accurate MOSFET I-V model and its application for delay analysis in Nano-CMOS circuits

Asish Kumar Sinha

2012

 

5.

Design and Implementation of Low-Voltage, Low-Power Self-Biased CMOS Threshold Voltage Extractor circuit

Rituparna Dasgupta

2012

Internal guide (JU)

6

Performance Analysis Of a Modified Karatsuba Multiplier And Its Application In Circular Convolution

Razia Sultana

2013

 

7

Performance Analysis Of Different Combinational Circuits Using Modified GDI Techniques

Debrupa Metia

2014

 

8

Design And Implementation of Double Byte Reed Solomon Encoder Using 45nm Technology

Madhuresh Suman

2015

 

9

FPGA Implementation of RS(255, 223) codec for deep space communication

Arunabha Patra, CU

2015

 

10

Design and implementation of RS(255, 223)   encoder and decoder in FPGA

Bappaditya Kuila

 

2015

 

11

Design and implementation of RS(47, 41) codec for intelligent home networking

Neha Chauhan

2016

 

12

Design and implementation of RS(255, 249) codec for DNA sequencing

Mandira Sahoo

2016

 

13

Double and Triple Adjacency ECC code for Fast Memory

Sayan Tripathy

2017

 

 

Ph.D

  1. Multi-bits Error correcting codes for high speed memories
  2. Error correcting codes for Flash memories

 

 

Sponsored Projects/Grants

1. Design and Implementation of Double and Triple Adjacent Error Correcting Codes for Static Random Memory, applied to DST, (SP/YO//2018/673).